High speed pattern generating method and high speed pattern generator using the method

ABSTRACT

A high speed pattern generating method by which a pattern signal having a speed higher than conventional speed can be generated using a sequence control part operating at a speed equivalent to a conventional speed and a high speed pattern generator for materializing the method are provided. A high speed pattern signal having a speed multiple of the number of multiplexing against an operation speed of the sequence control part is generated by generating multi-phase sub patterns from a plurality of sub pattern generating parts and by taking out for multiplexing the multi-phase sub patterns one phase by one phase by a multiplexing circuit. Further, an instruction memory of a pattern generator is uniquely arranged to materialize the high speed pattern generating method.

TECHNICAL FIELD

The present invention relates to a high speed pattern generating methodfor generating test pattern signals at high speed and a high speedpattern generator using this method which are useful in applicationthereof to a semiconductor device testing apparatus or the like, thesemiconductor device testing apparatus being arranged to test asemiconductor device formed as a semiconductor integrated circuit (IC),for instance, an IC memory, as to whether it is conformable (pass)article or unconformable (failure) article.

BACKGROUND ART

FIG. 1 shows an example of a semiconductor device testing apparatusconventionally used for testing a semiconductor device such as an ICmemory. As shown in the drawing, this semiconductor device testingapparatus includes a pattern generator 100, a data selector 200, adevice under test, for example, an IC 300, and a logical comparator 400.The pattern generator 100 comprises a sequence control part 110 and apattern generating part 120.

The sequence control part 110 comprises, as shown in FIG. 2, a programcounter controller 111, a program counter 112, an instruction memory113, a loop counter 114 and an initial value storing register 115. Theinstruction memory 113 comprises a sequence control instruction storagearea 113A and a pattern generating instruction storage area 113B, andthese storage areas 113A and 113B are accessed by an address signalsupplied from the program counter 112. When the sequence controlinstruction storage area 113A is accessed, a sequence controlinstruction is read out from the sequence control instruction storagearea 113A and then this sequence control instruction is supplied to theprogram counter controller 111 to be decoded therein and an address tobe accessed next is determined. This address is sent to the programcounter 112 from the program counter controller 111 and the programcounter 112 supplies an address signal for accessing the determinedaddress to the instruction memory 113. Then, a sequence controlinstruction to be next executed is read out from the instruction memory113. In such a way, every time one of the sequence control instructionsis sequentially read out from the instruction memory 113, the programcounter controller 111 determines an address to be next accessed inaccordance with a control instruction written in that sequence controlinstruction. The above operation is repeated so that a patterngenerating instruction is read out from the pattern generatinginstruction storage area 113B.

One of the reasons why a system for reading out a pattern generatinginstruction while determining an address to be next accessed inaccordance with a sequence control instruction is used as describedabove is that in case of using a system for programming patterngenerating instructions one step by one step to generate patternsignals, for example, there occurs a trouble in the system that theprogram becomes extensive and lengthy and hence a large amount of workand time are required for the programming.

Therefore, a programming method for generating a predetermined testpattern a predetermined number of times using a loop instruction isgenerally employed. In this method, at starting time of a patterngeneration, the number of loop times etc. are stored in the initialvalue storing register 115 for each loop instruction and when a loopinstruction is executed, the number of loop times is counted by the loopcounter 114. When the loop instruction is executed a predeterminednumber of times, the execution of the loop instruction is terminated andthen the process moves to an execution of the next loop instruction.

A pattern generating instruction read out from the pattern generatinginstruction storage area 113B is supplied to a pattern generating part120 and the pattern generating part 120 generates a test pattern signaland an address signal in accordance with the pattern generatinginstruction.

The data selector 200 selects an address signal and a data signal etc.to be applied to the IC under test 300 from the signals generated by thepattern generating part 120 and supplies those signals to the IC undertest 300 after shaping the wave forms. Also, the data selector 200selects an expected value data from the test pattern signals andsupplies the expected value data to the logical comparator 400.

In the logical comparator 400, a data read out from the IC under test300 is logically compared with an expected value data from the dataselector 200. When a mismatch is detected in the logical comparison, afailure of the IC under test is determined. Therefore, when a mismatchis not detected, the IC under test 300 can be judged as a good IC.Consequently, a pass/failure decision of the IC under test 300 can beperformed.

Since, in the conventional pattern generator 100, the instruction memory113 must be operated in a speed higher than the pattern generationfrequency, it is difficult to improve the sequence control part 110 forhigher speed operation. Particularly, in order to make the patterngeneration speed higher, all of the instruction memory 113, the programcounter controller 111, the program counter 112 and the loop counter 114etc. must be arranged using elements which allow a higher speedoperation. The pattern generating part 120 must also be arranged usinghigh speed operable elements and must take a super multi-stage pipelinestructure. Therefore, there is a shortcoming in operating the patterngenerator in high speed that a huge expense is necessary, and theequipment becomes expensive and large in physical size even if theequipment is realized.

In addition, even if the expenditure is possible, there is a limit inthe operation speed of the high speed operable element. Therefore, inthe prior art, it is difficult to increase the pattern generation speedof 100 MHz to several 100 MHz.

DISCLOSURE OF THE INVENTION

It is a first object of the present invention to provide a high speedpattern generator which can generate patterns at high speed that isseveral times the speed of a conventional pattern generator without needof using elements operable at high speed.

It is a second object of the present invention to provide a high speedpattern generator for which a program for generating patterns at highspeed can easily be created without requiring a special programmingtechnique for a high speed operation.

In accordance with a first aspect of the present invention, a high speedpattern generating method is provided which comprises the steps of:converting a series of pattern generating instructions disposed inaccordance with a pattern generation sequence to a series of multi-phasesub pattern generating instructions; generating multi-phase sub patternsignals based on this series of sub pattern generating instructions; andtime division multiplexing the multi-phase sub pattern signals so that atest pattern signal having an increased speed multiplied by the numberof multiplexing can be generated.

In accordance with a second aspect of the present invention, there isprovided a high speed pattern generator implementing the high speedpattern generating method according to the first aspect mentioned above.

It is to be noted that in case of implementing particularly the highspeed pattern generating method according to the first aspect, thereoccurs a trouble that sub pattern generating instructions havingdifferent contents lo must be written in the same address of theinstruction memory. The high speed pattern generator according to thesecond aspect of the present invention eliminates this trouble, asdescribed later, thereby to realize the high speed pattern generatingmethod according to the first aspect.

In accordance with a third aspect of the present invention, there isprovided a high speed pattern generating method which comprises thesteps of: outputting from an instruction memory a pattern generatinginstruction having an argument for prescribing a plurality of subpatterns subsequent to a main pattern; generating a main pattern from amain pattern generating part in accordance with the pattern generatinginstruction; supplying said main pattern generated from said mainpattern generating part to a plurality of sub pattern generating parts;changing said main pattern in said plurality of sub pattern generatingparts in accordance with said arguments; delaying said main patternthereby to generate a plurality of sub patterns subsequent to said mainpattern in the same phase as that of said main pattern; and timedivision multiplexing said main pattern and said plurality of subpatterns in a multiplexing circuit, and taking out the time divisionmultiplexed patterns so that high speed patterns changing in accordancewith a predetermined pattern generation sequence are generated.

In accordance with a fourth aspect of the present invention, there isprovided a high speed pattern generator which comprises an instructionmemory for storing a sequence control instruction and pattern generatinginstructions and generates a test pattern signal to be applied to adevice under test in accordance with a pattern generating instructionread out from the instruction memory, and is arranged such that a mainpattern generating instruction and arguments for defining sub patternsto be generated in a predetermined sequence subsequent to a main patternby changing the main pattern generating instruction are generated fromthe pattern generating instruction storage area of the instructionmemory, the pattern generating instruction is supplied to a main patterngenerating part to generate the main pattern from the main patterngenerating part, a plurality of sub patterns having respective orders tofollow the main pattern are generated from the main pattern in aplurality of sub pattern generating parts, and a high speed patternsignal can be generated by multiplexing the main pattern signal and subpattern signals in time division, whereby a high speed pattern signalcan be generated.

With the configuration of the high speed pattern generator of the fourthaspect, the circuits existing between the sequence control part and themultiplexing circuit for inputting the main pattern signal and the subpattern signals to the multiplexing circuit can be arranged usingcircuits which operate at the speed equivalent to the conventionalspeed. Moreover, even if these circuits are operated in the speedequivalent to the conventional speed, the pattern generating speed canbe increased to a speed multiplied by the number of multiplexing.Therefore, according to the present invention, there can be obtained abenefit that a high speed pattern generator can be provided at low cost.

In addition, with the configuration of the high speed pattern generatoraccording to the fourth aspect, since sub patterns are generated byadding an argument (parameter) to a main pattern generating instruction,a programmer may be able to create a program by only defining a mainpattern. Therefore, a pattern generating program can easily be created.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for explaining an arrangement of an example ofa conventional IC testing apparatus;

FIG. 2 is a block diagram for explaining a sequence control part used ina conventional IC testing apparatus;

FIG. 3 is a block diagram for explaining a first embodiment of a highspeed pattern generating method according to the present invention;

FIG. 4 is a flow chart for explaining the first embodiment of the highspeed pattern generating method according to the present invention;

FIG. 5 is a timing diagram for explaining an operation of an essentialpart of the first embodiment of the high speed pattern generatoraccording to the present invention;

FIGS. 6A and 6B are diagrams showing an example of a program forgenerating a pattern;

FIG. 7 is a diagram for explaining a relationship between sequencecontrol instructions and patterns, sub patterns when the program shownin FIG. 6 is executed;

FIG. 8 is a block diagram showing a specific example of a sequencecontrol part used in a second embodiment of the high speed patterngenerator according to the present invention;

FIG. 9 is a diagram for explaining an operation of the sequence controlpart shown in FIG. 8;

FIG. 10 is a block diagram showing a specific example of an addressconverting part shown in FIG. 8;

FIG. 11 is a circuit connection diagram showing a specific example of amultiplexing circuit used in the high speed pattern generator accordingto the present invention;

FIG. 12 is a block diagram for explaining a specific example of thesequence control part used in the high speed pattern generator accordingto the present invention;

FIG. 13 is a diagram for explaining an arrangement of an address spaceof an instruction memory used in the high speed pattern generator shownin FIG. 12;

FIG. 14 is a diagram for explaining an address converting operation ofthe high speed pattern generator shown in FIG. 12;

FIG. 15 is a block diagram for explaining a third embodiment of the highspeed pattern generator according to the present invention;

FIG. 16 is a block diagram for explaining an arrangement of the sequencecontrol part used in the high speed pattern generator shown in FIG. 15;

FIG. 17 is a diagram for explaining an example of a program for drivingthe sequence control part shown in FIG. 16;

FIG. 18 is a diagram for explaining a relationship between sequencecontrol instructions generated when the program shown in FIG. 17 isexecuted and patterns generated by these sequence control instructions;

FIG. 19 is a wave form diagram for explaining an operation or the highspeed pattern generator shown in FIG. 15;

FIG. 20 is a block diagram for explaining a specific example of a mainpattern generating part and a sub pattern generating part used in thehigh speed pattern generator shown in FIG. 15;

FIG. 21 is a block diagram for explaining a specific example of amultiplexing circuit used in the high speed pattern generator shown inFIG. 15; and

FIG. 22 is a wave form diagram for explaining an operation of themultiplexing circuit shown in FIG. 21.

BEST MODES FOR CARRYING OUT THE INVENTION

Now a first embodiment of the high speed pattern generating methodaccording to the present invention will be described beforehand withreference to FIG. 3.

In the present invention, a plurality of sub pattern generatinginstruction storage areas 113B₁ to 113B₄ are provided in an instructionmemory 113. In this example, a case is shown in which four sub patterngenerating instruction storage areas 113B₁ to 113B₄ are provided andfour-phase sub pattern generating instructions are generated. Further,the number of phases of the sub pattern generating instruction storageareas 113B₁ to 113B₄ is not limited to four and may be equal to orgreater than two. As explained before, the sequence control instructionstorage area 113A is provided in the instruction memory 113 in additionto the sub pattern generating instruction storage areas 113B₁ to 113B₄.It is the same as the conventional technique that an address to be nextaccessed in the instruction memory is determined by reading out asequence control instruction stored in the sequence control instructionstorage area 113A and a reading sequence of pattern generatinginstruction is controlled by the sequence control instruction.

The sub pattern generating instructions stored in the sub patterngenerating instruction storage areas 113B₁ to 113B₄ are transferred froman upper level computer for managing the testing apparatus and arewritten in the instruction memory 113. That is, a pattern programcreated in accordance with a pattern generation sequence intended by auser is converted into a multi-phase supporting program by a translationprogram for converting into a multi-phase program and the sub patterngenerating instructions converted into multi phases are transferred tothe instruction memory 113 of the testing apparatus to be storedtherein.

Next, the relationship between a pattern generating instruction and asub pattern generating instruction will be explained referring to FIG.4. In FIG. 4, a reference numeral 10 shows pattern generatinginstructions (PTN GEN INSTR) for patterns that a user intends togenerate, which are listed a step by a step. This example shows a casewherein the pattern generating instructions have been created such thata pattern generating instruction "X<0" for initializing X addresspattern to 0 is executed in step 1, a pattern generating instruction"X<X+1" for incrementing the X address pattern by one is executed in thenext step 2, the pattern generating instruction "X<X+1" is executed inthe succeeding steps 3 through 12, a pattern generating instruction"X<X-1" for decrementing the X pattern address by one is executed in thesubsequent steps 13 through 16, the pattern generating instruction"X<X+1" for incrementing the X address pattern by one is executed againin the subsequent steps 17 through 24, and the pattern generatinginstruction "X<X-1" is executed in the succeeding steps 25 through 28. Areference numeral 11 shows values of the X address patterns (values in Xaddress register) produced when the pattern generating instructions 10are executed. As shown in the X address patterns 11, in step 1 X=0 isgenerated at the X address pattern, the X address pattern issequentially incremented by one (+1) in each step of steps 2 to 12, theX address pattern is sequentially decremented by one (-1) in each stepof steps 13 to 16 after reaching X=11 in step 12, and once it isdecreased to X=7 in step 16, the X address pattern reaches X=15 in step24, and the X address pattern reaches X=11 in step 28. The illustrated Xaddress patterns shown in the drawing are supplied to an IC under testin the sequence of steps 1 to 28.

In addition to the X address patterns, there exists Y address patterns,Z address patterns, etc. in practice. However, only X address patternswill be explained herein.

Reference characters 12A, 12B, 12C and 12D in FIG. 4 show sub patterngenerating instructions (SUB PTN GEN INSTR). The method for convertingthe pattern generating instructions to sub pattern generatinginstructions 12A to 12D is as follows. Each of the pattern generatinginstructions 10 is assigned to each phase in the step basis in thesequence of pattern generation. Then the pattern generating instructionsof the number corresponding to the number of multiplexing phases aresummed (performs an algebraic calculation assuming that the registervalues are variables) going back toward upstream starting from theassigned pattern generating instruction to convert into the subpatterns.

That is, assuming that sub pattern generating instructions 12A arestored in the sub pattern generating instruction storage area 113B₁, subpattern generating instructions 12B are stored in the sub patterngenerating instruction storage area 113B₂, sub pattern generatinginstructions 12C are stored in the sub pattern generating instructionstorage area 113B₃ and sub pattern generating instructions 12D arestored in the sub pattern generating instruction storage area 113B₄, anda multiplexing is performed in the sequence of the sub patterngenerating instruction storage areas 113B₁, 113B₂, 113B₃ and 113B₄, thepattern generating instruction X<0 in step 1 is assigned to a subpattern generating instruction croup 12A. Since no pattern generatinginstruction exists before step 1, the composed sub pattern generatinginstruction 12A becomes x<0.

Then, the pattern generating instruction X<X+1 in step 2 is assigned tothe sub pattern generating instruction group 12B. In this case, sincethere is a pattern generating instruction X<0 before step 2, X<0 andX<X+1 are summed and a sub pattern generating instruction X<1 isobtained.

Then, the pattern generating instruction X<X+1 in step 3 is assigned tothe sub pattern generating instruction group 12C. Since there are apattern generating instruction X<0 in step 1 and a pattern generatinginstruction X<X+1 in step 2 before step 3, these pattern generatinginstructions and the pattern generating instruction X<X+1 in step 3 aresummed and a sub pattern generating instruction X<2 is obtained.

Then, the pattern generating instruction X<X+1 in step 4 is assigned tothe sub pattern generating instruction group 12D. Since there are apattern generating instruction X<0 in step 1, a pattern generatinginstruction X<X+1 in step 2 and a pattern generating instruction X<X+1in step 3 before step 4, these pattern generating instructions and thepattern generating instruction X<X+1 in step 4 are summed, i.e. fourpattern generating instructions the number of which is equal to thenumber of sub pattern generating instruction storage areas are summed,and a sub pattern generating instruction X<3 is obtained.

Further, (X=0), (X=1), (X=2), (X=3) and (X=4) shown in parentheses belowthe respective sub pattern generating instructions show the results ofthe X address pattern generations when the sub pattern generatinginstructions 12A to 12D are supplied to sub pattern generating parts120A to 120D. These X address patterns coincide respectively with the Xaddress patterns 11 obtained by executing the pattern generatinginstructions 10 shown in FIG. 4.

In step 5, the pattern generating instruction X<X+1 is assigned to thesub pattern generating instruction group 12A. This pattern generatinginstruction X<X+1 and the three pattern generating instructions X<X+1before step 5 are summed and a sub pattern generating instruction X<X+4is obtained as the sub pattern generating instruction 12A in step 5.

Similarly hereinafter, the pattern generating instructions X<X+1 of foursteps are summed to obtain a sub pattern generating instruction X<X+4for each of the steps up to 12. Since the pattern generating instructionis changed to X<X-4 in step 13, the sub pattern generating instruction12A becomes X<X+2. In step 14, the sub pattern generating instruction12B becomes X<X+0. In step 15, the sub pattern generating instruction12C becomes X<X-2. In step 16, the sub pattern generating instruction12D becomes X<X-4. in steps 17 to 20, since the pattern generatinginstruction in each step is X<X+1, the sub pattern generatinginstructions 12A to 12D are X<X-2, X<X-0, X<X+2 and X<X+4, respectively.

In steps 21 to 24, since a pattern generating instruction X<X+1continues, the sub pattern generating instructions 12A to 12D are X<X+4,X<X+4, X<X+4 and X<X+4 in the step sequence. In steps 25 to 28, sincethe pattern generating instruction changes to X<X-1, the sub patterngenerating instructions 12A to 12D change to X<X+2, X<X+0, X<X-2, andX<X-4, respectively.

The sub pattern generating instructions are executed and associated Xaddress patterns can be generated from the respective sub patterngenerating parts 120A to 120D by reading out the sub pattern generatinginstructions 12A to 12D step by step from the sub pattern generatinginstruction storage areas 113B₁ to 113B₄ respectively and by inputtingthem to the sub pattern generating parts 120A, 120B, 120C and 120Drespectively.

FIG. 5 shows a relationship between the sub pattern generatinginstructions read out from the sub pattern generating instructionstorage areas 113B₁ to 113B₄ and the X address patterns generated bythese sub pattern generating instructions in the sub pattern generatingparts 120A to 120D. At a period t-1 of a clock CP1, the sub patterngenerating instructions X<0, X<1, X<2 and X<3 are read out from the subpattern generating instruction storage areas 113B₁ to 113B₄respectively. These sub pattern generating instructions X<0 to X<3 aresupplied to the respective sub pattern generating parts 120A to 120D togenerate X address patterns X=0, X=1, X=2 and X=3 respectively. Bysupplying these X address patterns X=0, X=1, X=2 and X=3 to themultiplexing circuit 130 and by multiplexing the X address patterns intime division using a clock CP2 in the order of X=0, X=1, X=2 and X=3, ahigh speed pattern signal HIP having a frequency multiplied by thenumber of multiplexing as shown in FIG. 5D can be obtained.

At a period of the CP1, all the sub pattern generating instructions readout from the sub pattern generating instruction storage areas 113B₁ to113B₄ are X<X+4. When these sub pattern generating instructions X<X+4are executed in the sub pattern generating parts 120A to 120D, upon theexecution of X<X+4, X address patterns X=4, X=5, x=6 and X=7 areobtained as X=0, X=1, X=2 and X=3 have already been inputted at theprevious period t-1.

As is apparent from the above explanation, according to the high speedpattern generating method of the present invention, the sub patterngenerating instruction storage areas 113B₁ to 113B₄ the number of whichcorresponds to the number of multiplexing are provided in theinstruction memory 113, and the sub pattern generating instructions 12Ato 12D are read out from the plurality of sub pattern generatinginstruction storage areas 113B₁ to 113B₄ and are supplied to the subpattern generating parts 120A to 120D. In this arrangement, a high speedpattern signal HIP arrayed in the original sequence to be applied to anIC under test can be obtained by generating the multi-phase sub patternsand by multiplexing the multi-phase sub patterns in accordance with apredetermined sequence in the multiplexing circuit 130.

Therefore, even if the portion of the pattern generator up to themultiplexing circuit 130 is arranged using circuits which operate in thespeed equivalent to the speed of a conventional pattern generator, thehigh speed pattern signal HIP outputted from the multiplexing circuit130 is a high speed pattern signal having a speed multiple of the numberof multiplexing. That is, as in the embodiment mentioned above, when thenumber of multiplexing is N=4, a high speed pattern signal having fourtime speed can be obtained. When the reading speed of the sub patterngenerating instructions from the instruction memory 113 is 100 MHz, ahigh speed pattern signal having 400 MHz speed can by obtained.

Further, when the aforementioned sub pattern generating instructions arewritten in the instruction memory 113, a trouble occurs as describedbelow. That is, there is a sequence control instruction storage area113A in the instruction memory 113 in addition to the sub patterngenerating instruction storage areas 113B₁ to 113B₄. A sequence controlinstruction for determining an address for accessing the instructionmemory 113 next is written in the secuence control instruction storagearea 113A and the sequence control instruction is read out to determinean address for accessing next.

FIGS. 6A and 6B show a simple program example for generating a sequencecontrol instruction and a test pattern. START #0 is an instruction forinitializing the program counter 112 (refer to FIG. 2) to #0. PC=#0,PC=#1, . . . show the values of the program counter 112, i.e., theaddresses of the instruction memory 113. The sequence controlinstructions shown at the respective right sides of the PC=#0, PC=#1, .. . are stored in the addresses respectively. An NOP instruction iswritten in the address #0 of the sequence control instruction storagearea 113A (FIG. 1) of the instruction memory 113. The NOP instruction isan instruction for "adding +1 to the program counter value and executingthe next instruction".

Therefore, the program counter 112 outputs PC=#1 and LB1:LOOP1 LB1written in the address #1 of the sequence control instruction storagearea 113A of the instruction memory 113 is executed. LB1 is a label nameand LOOP1 is an instruction for repeatedly executing rows between theinstruction row and the row indicated by a label described following theinstruction a specified number of times. In the case of LB1:LOOP1 LB1,this instruction row is repeatedly executed a specified number of times.The specified number of times is stored in the initial value storingregister 115 shown in FIG. 2. When the loop is executed a specifiednumber of times, the loop counter 114 detects the state and the addressvalue outputted from the program counter 112 is incremented by one.

When, for example, "2" is stored in the initial value storing register115, the program counter 112 adds +1 to the address to be outputted andthe process moves to the next row after executing the LOOP1 instructiontwice. In the next row, an instruction LOOP2 LB1 written in address #2of the instruction memory 113 is executed. This instruction is aninstruction for executing LOOP2 once and then returning to the rowindicated by the label LB1. Actually, it is repeated that theinstruction LB1:LOOP1 LB1 is executed, for example, several hundredtimes and then the instruction LOOP2 is executed once.

On the other hand, the pattern generating instructions are written inthe test pattern generating instruction storage area 113B shown in FIGS.6A and 6B. Test patterns are generated by the pattern generatinginstructions read out from the addresses #0, #1, #2, . . . of theinstruction memory 113 determined by executing the sequence controlinstructions. In the case where a pattern generating instruction readout from the address #0 is A, a pattern generating instruction read outfrom the address #1 is B and a pattern generating instruction read outfrom the address #2 is C, when a sequence control instruction LOOP1 isexecuted twice and LOOP2 is executed once and then an operation toreturn to a label LB1 again is executed, the relationship between eachcycle, the address values (PC values) outputted from the address counter112, the sequence control instructions and the patterns A to C is shownin FIG. 7.

If the patterns A, B, C, . . . are independent patterns which do notmutually relate to, the pattern A may be written in address #0 of thepattern generating instruction storage area 113B, the pattern B may bewritten in address #1 and the pattern C may be written in address #2.

However, in order to perform multiplexing processes, as shown in FIG. 4,the sub pattern generating instructions 12Ato 12D may have to generatedifferent sub pattern generating instructions dependent on the patternsin the previous cycle even if the sub pattern generating instruction isread out by the same loop instruction. This state is shown in the columnof sub pattern in FIG. 7. In cycle 1, the sub pattern generatinginstruction A can be written in address #0 as no history exists. Incycle 2, a sub pattern A˜B which is determined by the pattern A of cycle1 and the pattern B described in that row is written in address #1.Similarly, the sub pattern of cycle 3 is B˜B, the sub pattern of cycle 4is B˜C, the sub pattern of cycle 5 is C˜B, the sub pattern of cycle 6 isB˜B, and the sub pattern of cycle 7 is B˜C.

As is apparent from the above description, the sub patterns A˜B, B˜B andC˜B generated in cycles 2, 3, 5 and 6 must be written in a same address#1. Such phenomena often occur, as shown in FIG. 6B, when operations forreturning to a common label LB1 from multiplexed loop instructions LOOP2to LOOP5 . . . are performed.

Further, when the historic indications A˜B, B˜B, B˜C . . . of subpatterns explained referring to FIG. 7 are applied to FIG. 4, the subpatterns A˜B generated in steps 5 to 8 and the sub patterns B˜Bgenerated in steps 9 to 12 look like the same pattern generatinginstruction because the sub pattern generating instructions are allX<x+4. However, the system must be arranged such that a normal operationcan always be performed wherever in steps 1 to 4, for example, aninitializing instruction X<0 is described by the user. Consequently,when X<0 is described in, for example, step 2, the sub patterngenerating instruction in step 5 becomes X<3. Therefore, the sub patterngenerating instructions for A˜B and B˜B must be treated as different subpattern generating instructions in accordance with the sub patternhistory.

As mentioned above, it will be understood that when sub patterns inmultiplexing process are written in an instruction memory, different subpattern generating instructions (referred to as pattern generatinginstructions of different kind, hereinafter) may have to be written inthe same address.

A first embodiment of a high speed pattern generator according to thepresent invention proposes, in order to resolve this trouble, a highspeed pattern generator wnich normally operates, by providing an addressconverting part to store pattern generating instructions of differentkind in different addresses.

FIG. 8 shows a specific example of a sequence control part 110 having anaddress converting part used in a high speed pattern generator. Samereference characters are assigned to the portions corresponding to thosein FIG. 2. The configuration characterized by the sequence control part110 is that the instruction memory 113 is divided into a firstinstruction memory 113-1 and a second instruction memory 113-2, anaddress to be supplied to the first instruction memory 113-1 isconverted into a different address in the address converting part 140,and the converted address is supplied to the second instruction memory113-2.

The sequence control instruction storage area 113A shown in FIG. 3 isprovided in the first instruction memory 113-1 and this sequence controlinstruction storage area 113A is accessed by an address signal ADR (#0,#1, #2, . . . ) outputted from the program counter 112. Sub patterngenerating instruction storage areas 113B₁, 113B₂, 113B₃ and 113B₄ areprovided in the second instruction memory 113-2. The address capacity ofthe second instruction memory 113-2 is selected to be larger than theaddress area of the first instruction memory 113-1, for example, doubleaddress area of the first instruction memory 113-1. By making theaddress area of the second instruction memory 113-2 double of the firstinstruction memory 113-1, an address area specified by addresses #0, #1,#2, #3, . . . outputted from the program counter 112 is secured in thefirst half of the address area of the second instruction memory 113-2.Further, the pattern generating instructions of different kind whichcannot be written in the addresses #0, #1, #2, #3, . . . may be writtenin the second half address area of the second instruction memory 113-2.

FIG. 10 shows a specific configuration of the address converting part140. The address converting part 140 can be arranged by address delaymeans 142 for delaying by one cycle an address signal outputted from theprogram counter 112, selector means 143 for selecting and taking outeither one of the address signal delayed by one cycle in the addressdelay means 142 or the address signal not delayed, and adding means 144for adding a predetermined value to the address signal outputted fromthe program counter 112 when the selector means selects the addresssignal delayed by one cycle. Further, in FIG. 10, the reference numerals141 and 145 indicate flip-flops for re-timing, respectively.

A control signal is supplied to a control terminal S of the selectormeans 143 from a control logic circuit 150 to select either one of theaddress signal delayed in the delay means 142 or the address signal notdelayed. After acquiring a sequence control instruction read out fromthe program counter controller 111 and the first instruction memory113-1, the control logic circuit 150 outputs a control signal which is alogical "0" when the address value outputted from the program counter112 changes to a value incremented by one, or the control logic circuit150 outputs a control signal which is a logical "1" when the addressvalue outputted from the program counter 112 is a value other than valueincremented by one. In the state where the control logic circuit 150outputs a logical "0", the selector means 143 selects the input terminalA and outputs the address signal outputted from the program counter 112as it is. When the control logic circuit 150 outputs a logical "1", theselector means 143 selects the input terminal B to select the addresssignal delayed by one cycle in the delay means 142 and then, outputs thedelayed address signal to the adding means 144. In the adding means 144,a predetermined value is added to the address signal outputted from theprogram counter 112 by adding the one bit of the control signaloutputted from the control logic circuit 150 to the upper bit portion ofthe address signal selected by the selector means 143. That is, theaddress area is increased to a double address area by adding one bit tothe upper bit portion of the address signal outputted from the programcounter 112. Thus, it becomes possible that sub pattern generatinginstructions (pattern generating instructions of different kind) whichcannot be written in the address area specified by the address signaloutputted from the program counter 112 are written in the address areaexpanded to double. In the example shown in FIG. 9, the value added inthe adding means 144 is #400 as the program counter 112 has 10 bits.

FIG. 9 shows the address converting operations when LOOP1 instruction isrepeated four times and LOOP2 instruction is repeated twice in theprogram example of FIG. 6A. When the address (PC) value outputted fromthe program counter 112 is incremented by one, the address IM2A of thesecond instruction memory 113-2 is not converted and the PC becomesPC=IM2A. In the case in which the PC value is other than a valueincremented by one, an address converting process for adding +#400 to aPC value delayed by one cycle is performed. Therefore, in the steps inwhich sub patterns are changed, every pattern generating instruction ofdifferent kind which is generated transitively can be stored in thesecond instruction memory 113-2 without any exception.

In this case, the address converting part 140 is arranged such that theselector means 143 selects an address signal delayed by one cycle whenan address value outputted from the program counter 112 changes to avalue other than a value incremented by one. Therefore, as in thepattern generation program shown in FIG. 6B, even if the process returnsfrom many loop instructions to LOOP1 specified by a label LB1, thepredetermined value #400 is added to the address where a loopinstruction executed in the previous cycle is described, to perform anaddress conversion. Consequently, even if the process returns to LOOP1from any one of the loop instructions, an address duplication will notoccur.

FIG. 11 shows a specific example of the multiplexing circuit 130. Subpatterns X=0, X=1, X=2 and X=4 (refer to FIG. 5) generated respectivelyby the sub pattern generating parts 120A, 120B, 120C and 120D of the subpattern generator 120 shown in FIG. 3 are supplied to input terminals A,B, C and D, respectively. Flip-flops FF₁, FF₂, FF₃ and FF₄ are coupledto the input terminals A, B, C and D, respectively. The clock CP1 shownin FIG. 5 is supplied to each clock input terminal CK of the flip-flopsFF₁ to FF₄. The sub patterns X=0, X=1, X=2 and X=3 are taken in theflip-flops FF₁ to FF₄ respectively in the period of the clock CP1.Outputs of the flip-flops FF₁ to FF₄ are coupled respectively to inputterminals T_(o) to T₃ of the multiplexer MUX. A count output of theclock CP2 (refer to FIG. 3) is supplied to a control input terminal S ofthe multiplexer MUX from a counter CTR. The four input terminals aresequentially switched to sequentially output the sub patterns X=0, X=1,X=2 and X=3 from an output terminal Q as shown in FIG. 5D. Thus, a highspeed pattern signal HIP is outputted. In the next cycle of the clockCP1, sub patterns X=4, X=5, X=6 and X=7 are inputted to the flip-flopsFF₁ to FF₄, respectively. These sub patterns are multiplexed andoutputted to the output terminal Q as a high speed pattern signal HIP.After that the above operation is repeated and a high speed patternsignal changing in a desired sequence can be generated.

FIG. 12 shows a second embodiment of the high speed pattern generatoraccording to the present invention. In this embodiment, a firstinstruction memory 113-1 and a second instruction memory 113-2 eachhaving 10 bit address are made of memories of the same address capacityrespectively. In the sequence in which a pattern generating instructionof different kind is generated, an address where its sequence controlinstruction is described is converted to an address which issequentially decremented every time by one starting from the lastaddress of the second instruction memory 113-2.

In this embodiment, an address converting table area 113-1A is providedin the first instruction memory 113-1 and address converting table dataare written in this area. An address converting table data is an addressvalue for storing a pattern generating instruction of different kindtransitively generated in the steps where sub patterns change. When asequence instruction such as LOOP instruction, etc. which performs anoperation other than an operation for incrementing the program counterby one is described in a pattern program, values of the addressconverting table data #3FF, #3FE, #3FD, #3FC, . . . which aredecremented by one in the occurrence sequence from the last address #3FFof the second instruction memory 113-2 are allocated by a translationprogram.

FIG. 13 shows the address allocation state in the first instructionmemory 113-1 and the second instruction memory 113-2. In the side of thefirst address #0 of the first instruction memory 113-1, sequence controlinstructions SA, SB, SC and SD are written in the addresses specifiedfor the sequence control instructions sequentially from #0. The sequencecontrol instructions SA, SB, SC and SD such as LOOP instructions, etc.each of which performs an operation other than an operation forincrementing the program counter by one are also written in theinstruction memory 113-1 without any exception. Sub pattern generatinginstructions are written in the same addresses of the second instructionmemory 113-2 as those of the first instruction memory. Further, patterngenerating instructions of different kind such as LOOP instructions,etc. corresponding to the sequence control instructions SA, SB, SC andSD each of which performs an operation other than an operation forincrementing the program counter by one are written in the side of thelast address of the second instruction memory 113-2, i.e., in the orderof #3FF, #3FE, #3FD, #3FC, . . . in this example.

Either one of a converted address signal outputted from the addressconverting table area 113-1A or an address signal outputted from theprogram counter 112 is selected by the selector means 143 and issupplied to the second instruction memory 113-2. The converted addresssignal outputted from the address converting table area 113-1A isdelayed by one cycle in the address delay means 142 and is inputted tothe selector means 143. The selector means 143 is controlled by acontrol signal of the same control logic circuit 150 as explained withreference to FIG. 10.

FIG. 14 shows an address conversion result when LOOP1 instruction isrepeated four times and LOOP2 instruction is repeated twice. In thiscase, as shown in cycle 7, when the program counter changes to a valueother than a value incremented by one, #3FE which is converted from theaddress #2 of the previous cycle is delayed in the address delay means142 and is supplied to the second instruction memory. After that, #3FFwhich is converted from #1 where a sequence control instruction is readout in cycle 7 is supplied to the second instruction memory. Therefore,by this operation, even in the case where the process returns to a sameloop from many loops as shown in FIG. 6B, duplicated addresses are notgenerated.

Similarly to the embodiment explained with reference to FIG. 10, withthe arrangement shown in FIG. 14, pattern generating instructions ofdifferent kind can also be stored in the second instruction memory 113-2and be read out therefrom.

Next, a second embodiment of the high speed pattern generating methodaccording to the present invention and a third embodiment of the highspeed pattern generator according to the present invention will beexplained with reference to FIG. 15. As shown in FIG. 15, the high speedpattern generator 130 in the third embodiment comprises a sequencecontrol part 110, a pattern generating part 120 and a multiplexingcircuit 500 for multiplexing in time division the test patternsgenerated by the pattern generating part 120. That is, in thisembodiment, an arrangement for obtaining a high speed pattern signal bymultiplexing is employed. Therefore, pattern signals distributed to thenumber of paths corresponding to the number of multiplexing must begenerated. Consequently, in this embodiment, a main pattern generatinginstruction MAIN and arguments (parameters) P1, P2 and P3 for definingpredetermined patterns following the main pattern are generated from thesequence control part 110 at every sequence control.

The main pattern generating instruction MAIN is inputted to a mainpattern generating part 121 to generate a main pattern. On the otherhand, the parameters P1, P2 and P3 are supplied to respective subpattern generating parts 122, 123 and 124. The main pattern generatedfrom the main pattern generating part 121 is also supplied to these subpattern generating parts 122, 123 and 124. These sub pattern generatingparts 122, 123 and 124 generate patterns to be applied to an IC undertest 300 in the sequence following the main pattern based on the mainpattern using the parameters P1, P2 and P3.

The constitution and operation of each part will be now explained indetail.

The sequence control part 110 comprises, similarly to the conventionalexample shown in FIG. 2, a program counter controller 111, a programcounter 112, an instruction memory 113, a loop counter 114 and aninitial value storing register 115. However, as shown in FIG. 16, thesequence control part 110 in this case is different from theconventional example in the point that a main pattern generatinginstruction MAIN and a plurality of parameters P1, P2 and P3 aregenerated from the pattern generating instruction storage area 113B ofthe instruction memory 113 for every sequence control instruction.

FIG. 17 shows an example of a pattern program for generating the patterngenerating instructions. START #0 means that the pattern generation isstarted from the first address outputted from the program counter 112.NOP is executed at address #0. NOP means that the address is incrementedby one. Therefore, the address is changed to #1 in the next row. In thesecond row, repetitive executions of the label LB1 are effected by thenumber of times N specified by loop instruction LOOP1. The repetitivetimes N is defined by a set value stored in the initial value storingregister 115.

X<0 (1, 2, 3) and X<X+4 (1, 2, 3) described in the first row and thesecond row respectively are the pattern generating instructions. In thiscase, X<0 and X<X+4 represent main pattern generating instructions. X<0is an instruction for initializing the X address register to 0, and X<+4is an instruction for adding +4 to a value of the X address register andfor storing the calculation result in the X address register. Thenumerals in (1, 2, 3) indicate values of parameters P1, P2 and P3,respectively, and are added to the main pattern in the sub patterngenerating parts 122, 123 and 124, respectively.

FIG. 18 shows, when the pattern program shown in FIG. 17 is executed,the relationship between a main pattern generating instruction MAIN, amain pattern generated by the main pattern generating instruction MAINand sub patterns generated by the sub pattern generating parts 122 to124.

When a main pattern generating instruction is supplied to the mainpattern generating part 121 shown in FIG. 15 and parameters P1, P2 andP3 are supplied to the sub pattern generating parts 122, 123 and 124,respectively, the main pattern generating parts 121 outputs X=0 as an Xaddress pattern and the sub pattern generating parts 122, 123 and 124output X=0+1, X=0+2 and X=0+3, respectively. FIG. 18 shows a case inwhich the loop instruction LOOP1 shown in FIG. 17 is repeated ten times.Therefore, the pattern generating instructions generated in steps 2 to11 shown in FIG. 18 generate X<X+4 (1, 2, 3) described in the loopinstruction LOOP1. When this pattern generating instruction X<X+4 issupplied to the main pattern generating part 121, the main patterngenerating part 121 outputs X=4 as a main pattern and the sub patterngenerating parts 122, 123 and 124 output patterns X=4+1, X=4+2 and X=4+3respectively as shown in the second cycle t in FIG. 19.

In such a way, the main pattern generating part 121 and the sub patterngenerating parts 122, 123, 124 output step after step groups ofcontinuous patterns X=1, X=2, X=3; X=5, X=6, X=7; and X=9, X=10, X=11respectively following main patterns X=0, X=4, X=8, . . .

FIG. 20 shows a specific embodiment of the main pattern generating part121 and the sub pattern generating parts 122, 123 and 124. The mainpattern generating part 121 can be arranged by four registers REG1,REG2, REG3 and REG4, an adder ALU, two multiplexers MUX1 and MUX2, and amask gate MASK.

A main pattern generating instruction X<0 or X<x+4 or the like isinputted to the register REG1 of the main pattern generating part 121from the sequence control pars 110 and a value of X is stored therein. Aparameter 0 from the sequence control part 110 is stored in the registerREG2 of the main pattern generating part 121. The multiplexer MUX1initially selects the register REG1 and the value of X stored in theregister REG1 is added to a value stored in the register REG2 and thenthe added result is stored in the register REG3. When the patterngenerating instruction is X<0, X is initialized to 0 and is stored inthe register REG1. Therefore, the adder ALU calculates X=0+0 and X=0 isstored in the register REG3. The value of X stored in the register REG3is sent to a pattern delay circuit 125 via the multiplexer MUX 2 and themask gate MASK, and is outputted to an output terminal TA after beingappropriately delayed. Further, the maximum value of the pattern to beapplied to an IC under test 300 is set in the register REG4. When thevalue of the register REG3 exceeds the value of the register REG4, themask gate MASK inhibits that a value greater than the set value in theregister REG4 is applied to an IC under test 300. The pattern delaycircuit 125 is provided in order to delay a test pattern generated bythe main pattern generating part 121 by the same delay time as the delaytime in the sub pattern generating parts 122, 123 and 124, thereby tooutput the test patterns to output terminals TA to TD in the same phase.

When a pattern generating instruction X<X+4 is inputted to the registerREG1 of the main pattern generating part 121, X=4 is stored in theregister REG1. As a result, the adder ALU calculates X=4+0 and thecalculation result is stored in the register REG3. Therefore, the mainpattern becomes X=4.

Next, the constitution and operation of the sub pattern generating parts122 to 124 will be explained. Since the sub pattern generating parts 122to 124 have the same configuration, only one sub pattern generating part122 will be explained herein. This sub pattern generating part 122comprises three registers REG2, REG3 and REG4, two multiplexers MUX1 andMUX2, and a masking gate MASK. The main patterns X=0, X=4, X=8, . . .generated by the main pattern generating part 121 are inputted to themultiplexer MUX1. The parameter P1 is inputted to the register REG2 fromthe sequence control part 110 (FIG. 16). In this examples a case of P1=1is shown. This parameter P1=1 is stored in the register REG2. (Theparameters 2 and 3 are stored in the registers REG2 of the sub patterngenerating parts 123 and 124 respectively.) When the main patterngenerating part 121 generates a main pattern X=0, the adder ALUcalculates X=0+1 and the calculation result X=1 is stored in theregister REG3. Therefore, a sub pattern X=1 is outputted to an outputterminal TB. Then, when the main pattern generating part 121 generates amain pattern X=4, the adder ALU of the sub pattern generating part 122calculates X=4+1 and the calculation result is stored in the registerREG3. As a result, a sub pattern X=5 is outputted to the output terminalTB. In such a way, in the sub pattern generating parts 122 to 124, theparameters (1, 2, 3) stored in the register REG2 are added to the mainpattern signals X=0, X=4, X=8, . . . generated from the main patterngenerating part 121 in the respective steps 1, 2, 3, . . . , and patternsignals X=0, X=1, X=2, X=3; X=4, X=5, X=6, X=7; and X=8, X=9, X=10, X=11arranged in the desired sequence are outputted to the output terminalsTA to TD for each of the respective cycles t-1, t, t+1, . . .

The patterns outputted from the output terminals TA to TD are inputtedto respective input terminals IA to ID of the multiplexing circuit 500shown in FIG. 21. In the multiplexing circuit 500, flip-flops 501, 502,503 and 504 are coupled to the input terminals IA, IB, IC and ID,respectively. The patterns, for example, X=0, X=1, X=2 and X=3 generatedfrom the pattern generating part 120 are respectively latched in theflip-flops 501 to 504 by a clock CLK1 shown in FIG. 22A. In amultiplexer 506 which is of a type having four inputs and one output,the latch outputs of the flip-flops 501 to 504 are selected and takenout in the period of a clock CLK2 shown in FIG. 22C. Further, theselatch outputs are then time adjusted by a flip-flop 507 and areoutputted to an output terminal TQ. A high speed pattern signal HIPhaving an increased speed by four times, shown in FIG. 22D, is outputtedto the output terminal TQ in accordance with the predetermined sequence.Further, a reference numeral 505 shown in FIG. 21 indicates a counterfor counting the clock CLK2, and the multiplexer 506 is controlled forits switching by the count output of the counter 505.

As explained above, according to the present invention, while a sequencecontrol part and a pattern generating part operating in the speedequivalent to the conventional operation speed are utilized, a highspeed pattern signal having an increased speed in which the conventionaloperation speed is multiplied by the number of multiplexing can beobtained. Therefore, a high speed operation can be achieved without needof constituting the circuits using elements especially operating at highspeed. In addition, since a high speed operation can be achieved withoutemploying a super pipeline structure, there can be provided a high speedpattern generator which is manufactured at low cost and is compact.

Furthermore, a user may create a program (a pattern program) forgenerating patterns in the manner similar to the conventional way andmay not have to create a special program for multiplexing. Consequently,a program for generating a high speed pattern can be easily created.

In addition, according to the high speed pattern generator of the thirdembodiment of the present invention, even if the sequence control part110, the pattern generating part 120, and the flip-flops 501 to 504forming the multiplexing circuit 500 are constituted by circuitsoperating at a speed equivalent to the conventional operation speed, ahigh speed pattern signal having an increased speed multiplied by thenumber of multiplexing in the multiplexer 500 can be generated.Therefore, when, in the multiplexing circuit 500, the number ofmultiplexing N is selected to be N=4 as in the above embodiment, use ofcircuits operating at speed of 100 MHz results in generation of a highspeed pattern signal having speed of 400 MHz.

In addition, according to the present invention, since arguments(parameters) are added to a main pattern generating instruction and subpatterns to be multiplexed are generated using the arguments, aprogrammer can create a program by defining only the main pattern.Therefore, there is obtained an advantage that a program for generatinghigh speed patterns can easily be created.

Furthermore, according to the present invention, the apparatus can bemanufactured at low cost as the main portions of the sequence controlpart 110 and the pattern generating part 120, etc. can be composed ofcircuits equivalent to the conventional circuits. In addition, there isalso an advantage that the entire apparatus can be manufactured incompact size because a super multi-stage pipeline structure need not betaken.

What is claimed is:
 1. A high speed pattern generator comprising:apattern generator having a sequence control part and a patterngenerating part, the sequence control part including an instructionmemory and an address converting part, whereinthe instruction memory isdivided into a first instruction memory in which sequence controlinstructions are stored and a second instruction memory comprising aplurality of sub-pattern generating instruction storage areas in which aplurality of sub-pattern generating instructions are storedrespectively; an address signal for accessing the first instructionmemory is supplied to the second instruction memory via the addressconverting part; and the address converting part is arranged such thatwhen an address value of the address signal for accessing to the firstinstruction memory is changed toward a value incremented by one, theaddress converting part supplies the address signal the address value ofwhich has been changed to the second instruction memory, and when anaddress value of the address signal for accessing to the firstinstruction memory is changed to a value other than a value incrementedby one, the address converting part converts the address signal to aconverted address signal having a value in which a predetermined valueis added to an address value of such a preceding address signal which isin the immediately preceding cycle of the address signal for accessingto the first instruction memory, and supplies the thus converted addresssignal to the second instruction memory.
 2. The high speed patterngenerator according to claim 1 wherein said address converting partcomprises:address delay means for delaying by one cycle the addresssignal for accessing to said first instruction memory; selector meansfor selecting and taking out either one of a delayed address signaldelayed by said address delay means and an address signal which does notpass through said delay means; and adding means for adding, when saidselector means selects the delayed address signal delayed by said delaymeans, a predetermined value to the selected delayed address signal. 3.The high speed pattern generator according to claim 2 wherein a controlsignal of logical "0" is outputted when the address value of the addresssignal for accessing to said first instruction memory is changed towarda value incremented by one is detected, and a control signal of logical"1" is outputted when the address value of the address signal foraccessing to said first instruction memory is changed to a value otherthan a value incremented by one is detected, said control signal oflogical "1" controlling said selector means forming said addressconverting part so that said selector means selects the delayed addresssignal outputted from said address delay means, and said adding meansadds said control signal of logical "1" to the most significant bit sideof the selected delayed address signal to execute an address conversion.4. The high speed pattern generator according to claim 3, furthercomprising:address delay means for delaying by one cycle a convertedaddress outputted from said address converting table; and selector meansfor selecting either one of a delayed address delayed by said addressdelay means and an address signal for accessing to said firstinstruction memory to supply the selected one to said second instructionmemory, and wherein said selector means supplies, when an address valueof the address signal for accessing to said first instruction memory ischanged toward a value incremented by one, the address signal theaddress value of which has been changed to said second instructionmemory, and supplies, when an address value of said first instructionmemory is changed to a value other than a value incremented by one, adelayed address signal delayed by said address delay means to saidsecond instruction memory.
 5. The high speed pattern generator accordingto claim 4, further comprising a control logic circuit for controllingsaid selector means, when detects that a value of the address signal foraccessing to said first instruction memory is changed toward a valueincremented by one, so that said selector means selects the addresssignal for accessing to said first instruction memory and supplies theselected address signal to said second instruction memory, and forcontrolling said selector means, when detects that a value of theaddress signal for accessing to said first instruction memory is changedto a value other than a value incremented by one, so that said selectormeans selects the converted address outputted from said addressconverting table and supplies the selected converted address to saidfirst instruction memory.
 6. A high speed pattern generating method forgenerating test pattern signals at high speed from a pattern generatorwhich comprises a sequence control part and a pattern generating partand generates a test pattern signal from said pattern generating part inaccordance with a pattern generating instruction read out from aninstruction memory provided in said sequence control part, said testpattern signal being applied to a device under test for testing theoperation thereof, said method comprising the steps of:providing Nsub-pattern generating instruction storage areas for storing Nsub-pattern generating instructions in said instruction memory, which isprovided in said sequence control part, where N is an integer greaterthan or equal to 2; supplying said N-sub-pattern generating instructionsread out from said N sub-pattern generating instruction storage areas toN sub-pattern generating part which are provided in said N sub-patterngenerating part to receive corresponding one of the respective Nsub-pattern generating instructions thus supplied thereto, respectively;generating a multi-N-phase pattern signal comprising the N sub-patternsignals having different phases generated from said N sub-patterngenerating parts in accordance with the N sub-pattern generatinginstructions supplied thereto, respectively, said multi-N-phase patternsignal being distributed in phases and in the sequence to be applied tosaid device under test; and time division multiplexing by 1/N saidmulti-N-phase pattern signal using a multiplexing circuit therebygenerating the high speed pattern signal having an increased speedmultiplexed by N, wherein said instruction memory is divided into afirst instruction memory in which sequence control instructions and anaddress converting table are stored, and a second instruction memorycomprising a plurality of pattern generating instruction storage areasand said address converting table converts, when an address value of theaddress signal for accessing to said first instruction memory is changedtoward a value other than a value incremented by one in accordance witha sequence control instruction, the address value of said firstinstruction memory into which that sequence control instruction isstored into an address value sequentially decremented by one from thelast address of said second instruction memory and outputs the convertedaddress signal, and supplies, when and address value of the addresssignal for accessing to said first instruction memory is changed towarda value incremented by one, the address signal as it is to said secondinstruction memory, and supplies, when an address value of the addresssignal for accessing to said first instruction memory is changed to avalue other than a value incremented by one, the converted addressoutputted from said address converting table to said second instructionmemory.
 7. A high speed pattern generating method for generating testpattern signals at high speed, being characterized by the stepsof:outputting from an instruction memory a pattern generatinginstruction having an argument for prescribing a plurality of subpatterns following a main pattern; generating a main pattern from a mainpattern generating part in accordance with the pattern generatinginstruction; supplying said main pattern generated from said mainpattern generating part to a plurality of sub pattern generating parts;changing said main pattern in said plurality of sub pattern generatingparts in accordance with said arguments; delaying said main patternthereby to generate a plurality of sub patterns subsequent to said mainpattern in the same phase as that of said main pattern; and timedivision multiplexing said main pattern and said plurality of subpatterns in a multiplexing circuit, and taking out the time divisionmultiplexed patterns so that high speed patterns changing in accordancewith a predetermined pattern generation sequence are generated.
 8. Ahigh speed pattern generator used in a semiconductor device testingapparatus for testing the operation of a device under test by generatinga test pattern signal from a pattern generating part in accordance withpattern generating instructions read out from an instruction memoryprovided in a sequence control part and by applying the test patternsignal to the device under test,said high speed pattern generator beingcharacterized in that:a main pattern generating instruction forgenerating a main pattern and arguments for prescribing a plurality ofpatterns to be generated in a predetermined sequence subsequent to themain pattern are read out from said instruction memory; the main patternis generated from said main pattern generating part in accordance withsaid read out main pattern generating instruction; the main patterngenerated from said main pattern generating part is supplied to aplurality of sub pattern generating parts; a plurality of sub patternscorresponding to the plurality of patterns to be generated in thepredetermined sequence subsequent to the main pattern are generated inaccordance with said arguments in said plurality of sub patterngenerating parts; and said plurality of sub patterns and said mainpattern are time division multiplexed in a multiplexing circuit so thathigh speed patterns having an increased speed in which the number ofmultiplexing in said multiplexing circuit is multiplied by the speed ofreading out said pattern generating instructions are generated.
 9. Thehigh speed pattern generator according to claim 8, being characterizedin that the main pattern generated from said main pattern generatingpart is delayed by an amount of delay time equivalent to that in saidsub pattern generating parts so that the phase of said main pattern andthe phases of the sub patterns generated from said plurality of subpattern generating parts are matched by this delay operation, and saidmain pattern and said sub patterns the phases of which are matched withone another are supplied to said multiplexing circuit.
 10. A high speedpattern generator comprising:a sequence control part; and a patterngenerating part, wherein said sequence control part comprises:aninstruction memory which comprises a first instruction memory storingsequence control instructions and a second instruction memory having Nsub-pattern generating instruction storage areas storing N sub-patterngenerating instructions, where N is an integer greater than or equal to2; a program counter generating an address signal accessing said firstinstruction memory; and an address converting part supplied with theaddress signal from said program counter and supplying a convertedaddress signal to said second instruction memory; said addressconverting part being arranged such that when an address value of theaddress signal accessing said first instruction memory is changed to avalue incremented by one, said address converting part supplies theaddress signal, the address value of which has been changed to saidsecond instruction memory, and when an address value of the addresssignal accessing said first instruction memory is changed to a valueother than a value incremented by one, said address converting partconverts the address signal to an address signal having a value in whicha predetermined value is added to an address in an immediately precedingcycle of the address signal accessing said first instruction memory, andsupplies the converted address signal to said second instruction memory.11. The high speed pattern generator according to claim 10, wherein saidaddress converting part comprises:address delay means for delaying byone cycle the address signal for accessing said first instructionmemory; selector means for selecting and taking out either one of adelayed address signal delayed by said address delay means and anaddress signal which does not pass through said delay means; and addingmeans for adding, when said selector means selects the delayed addresssignal delayed by said delay means, a predetermined value to theselected delayed address signal.
 12. The high speed pattern generatoraccording to claim 11, further comprising a control logic circuit whichdetects the address value of the address signal and outputs a controlsignal of logical "Y" when the address value is a value incremented byone, and a control signal of logical "1" when the address value is avalue other than the value incremented by one, whereinsaid selectormeans selects the delayed address signal output from said address delaymeans when said control signal of logical "1" is supplied thereto, andsaid adding means adds said control signal of logical "V" to a mostsignificant bit side of the selected delayed address signal to executean address conversion.
 13. The high speed pattern generator according toclaim 12, further comprising:address delay means for delaying by onecycle a converted address signal output in accordance with said addressconverting table; and selector means for selecting either one of thedelayed converted address signal delayed by said address delay means andan address signal for accessing said first instruction memory to supplythe selected one to said second instruction memory, wherein saidselector means supplies, when an address value of the address signal foraccessing said first instruction memory is changed to a valueincremented by one, the address signal, the address value of which hasbeen changed to said second instruction memory, and supplies, when anaddress value of said first instruction memory is changed to a valueother than a value incremented by one, the delayed converted addresssignal delayed by said address delay means to said second instructionmemory.
 14. A high speed pattern generator comprising:a sequence controlpart; a pattern generating part; and a multiplexing circuit, whereinsaid sequence control part comprises:a first instruction memory having asequence control instruction storage area storing sequence controlinstructions and an address converting table storage area storing anaddress converting table, a second instruction memory having Nsub-pattern generating instruction storage areas storing respective oneof sub-pattern generating instructions, respectively, where N is aninteger greater than or equal to 2, and a selector, whereinsaid addressconverting table storage area of said first instruction memory convertsin accordance with said address converting table, when an address valueof the address signal for accessing said first instruction memory ischanged to a value other than a value incremented by one, which changeis caused by a sequence control instruction, the address value of saidaddress signal for said first instruction memory which corresponds tothe address in which said sequence control instruction is stored into aconverted address signal which has an address value with sequentialdecrement by one from a last address of said second instruction memory,and outputs the converted address signal, and said selector supplies,when an address value of the address signal for accessing said firstinstruction memory is changed to a value incremented by one, the addresssignal for the first instruction memory to said second instructionmemory, and supplies, when the change in the address value of theaddress signal for accessing said first instruction memory is changed toa value other than a value incremented by one, the converted addresssignal output from said address converting table storage area to saidsecond instruction memory.
 15. The high speed pattern generatoraccording to claim 14, further comprising a control logic circuitcontrolling said selector means, when it is detected that a value of theaddress signal for accessing said first instruction memory is changed toa value incremented by one, so that said selector means selects theaddress signal for accessing said first instruction memory and suppliesthe selected address signal to said second instruction memory, andcontrolling said selector means, when it is detected that a value of theaddress signal for accessing said first instruction memory is changed toa value other than a value incremented by one, so that said selectormeans selects the converted address signal output from said addressconverting table and supplies the selected converted address signal tosaid first instruction memory.
 16. A high speed pattern generatingmethod comprising the steps of:outputting from an instruction memory amain pattern generating instruction and N arguments for prescribing Nsub-patterns which are to be generated subsequent to the main pattern,respectively, where N is an integer greater than or equal to 2;generating a main pattern by a main pattern generating part inaccordance with the main pattern generating instruction; supplying saidmain pattern generated from said main pattern generating part to Nsub-pattern generating parts, respectively; supplying respective one ofsaid N arguments from said instruction memory to corresponding one ofsaid N sub-pattern generating parts, respectively; generating Nsub-patterns by the N sub-pattern generating parts by changing said mainpattern in accordance with the argument supplied thereto, respectively;delaying said main pattern to match a main pattern phase with the phasesof said N sub-patterns, which are generated to be subsequent to saidmain pattern; and time division multiplexing by 1/N said main patternand said N sub-patterns in a multiplexing circuit; and removing the timedivision multiplexed patterns as an output pattern signal changing inaccordance with a predetermined pattern generation sequence with anincreased speed multiplexed by N.
 17. A high speed pattern generatorcomprising:a sequence control part; a pattern generating part; and amultiplexing circuit, whereinsaid sequence control part includes aninstruction memory storing a main pattern generating instructiongenerating a main pattern and arguments prescribing N sub-patterns to begenerated in a predetermined sequence subsequent to the main pattern,where N is an integer greater than or equal to 2, said patterngenerating part comprises a main pattern generating part generating amain pattern in accordance with the main pattern generating instructionsread out from the instruction memory and N sub-pattern generating partssupplied corresponding to one of the respective arguments, respectively,each of said N sub-pattern generating parts is further supplied with themain pattern generated by said main pattern generating part so that Nsub-patterns corresponding to the plurality of patterns to be generatedin the predetermined sequence subsequent to the main pattern aregenerated in accordance with said arguments by said N sub-patterngenerating parts, and said multiplexing circuit performs time divisionmultiplexing by 1/N onto said N sub-patterns and said main pattern sothat high speed patterns having an increased speed multiplied by N aregenerated.
 18. The high speed pattern generator according to claim 17,wherein said pattern generating part further comprises a pattern delaycircuit delaying the main pattern generated from said main patterngenerating part by an amount of delay time equivalent to that in saidsub-pattern generating parts so that a phase of said main pattern andphases of the N sub-patterns generated from said N sub-patterngenerating parts are matched by the delay operation and said mainpattern and said sub-patterns, the phases of which are matched with oneanother, are supplied to said multiplexing circuit.
 19. A high speedpattern generator comprising:a sequence control part which includes,aninstruction memory, a program counter supplying an address signal tosaid instruction memory, and an address converting part; a patterngenerating part; and a multiplexing part; said instruction memorycomprising:a first instruction memory having a sequence controlinstruction storage area storing sequence control instructions; and asecond instruction memory having N sub-pattern generating instructionstorage areas, where N is an integer equal to or greater than 2, storingN-phase sub-pattern generating instructions capable of providing N-phasesub-patterns; and said first instruction memory is accessed with anaddress signal supplied thereto from the program counter deriving asequence control instruction so that the read out sequence controlinstruction determines an address to be accessed next in the instructionmemory, said second instruction memory is accessed with an addresssignal supplied thereto from the program counter controlling a readoutsequence of the N-phase sub-pattern generating instructions from said Nsub-pattern generating instruction storage areas, said addressconverting part receiving the address signals from said program counteris arranged such that when an address value of one address signalsupplied thereto has a value incremented by one from that of a previousone address signal supplied thereto in an immediately preceding oneaccess cycle, said address converting part supplies said one addresssignal supplied thereto to said second instruction memory, and when anaddress value of one address signal supplied thereto has a value otherthan the value incremented by one from that of a previous one addresssignal supplied thereto in immediately preceding one access cycle, saidaddress converting part converts said previous one address signal into aconverted address signal by adding thereto a predetermined value andsupplies the converted address signal to said second instruction memory.20. The high speed pattern generator according to claim 19, wherein saidpattern generating part comprises:N-phase sub-pattern generating partswhich are supplied with N-phase sub-pattern generating instructions andgenerate N-phase sub-patterns.
 21. The high speed pattern generatoraccording to claim 20, wherein said multiplexing part comprises:Nflip-flop circuits, to which the N-phase sub-patterns are coincidentallyinput from said N-phase sub-pattern generating parts, respectively, andwhich takes therein the supplied N-phase sub-patterns in a period of afirst clock which is used for reading out of the sub-pattern generatinginstructions from the sub-pattern generating instruction storage areas;and a multiplexer, to which the thus taken N-phase sub-patterns areinput from the N flip-flop circuits, and which sequentially switchessaid N-phase sub-patterns in response to a second clock having a periodof 1/N of that of said first clock, to thereby obtain a high speedpattern signal having an increased frequency multiplied by N than thatof the first clock.
 22. The high speed pattern generator according toclaim 19, wherein said address converting part comprises:an addressdelay unit delaying by one cycle the address signal to be supplied fromsaid program counter to said first instruction memory and outputting aprevious address signal; a selector unit selecting and taking out eitherone of a delayed address signal delayed by said address delay means andan address signal which does not pass through said delay means; andadding means for adding, when said selector means selects the delayedaddress signal delayed by said delay means, a predetermined value to theselected delayed address signal.